1. Field of the Invention
The present invention relates to a clock tree synthesis and, more particularly, to a clock tree synthesis for low power consumption and low clock skew.
2. Description of Related Art
In the modem high speed VLSI design era, clock design plays a crucial role in determining chip performance and facilitating timing and design convergence. Clock routing is important in the layout design of a synchronous digital system as it influences correctness, area, speed and power dissipation of the synthesized system [reference 1 and 2]. Drastically increased requirements for high performance and high speed VLSI circuits have posed challenges to the design of high speed clock networks, where minimization of clock delay and clock skew has been a critical problem. So some circuit designers' inclination is toward developing techniques to minimize the power dissipation, the clock delay (latency) and the clock skew as well as developed, understood design and verification flows.
Buffer operations are widely used in designing clock distributed networks [reference 3]. Buffers can decouple capacitance to reduce equivalent loading of each wire, so rise time and wire delay could be reduced. Also, when the signal's transfer time is faster, it can reduce power consumption. Several methodologies are adopted in the power consumption and the clock skew minimization. The previous research inserts the buffers and constructs a H-tree to reach the optimization solution in both circuit area and the power consumption aspects [reference 4]. The balanced buffer insertion scheme attempts to partition the clock tree into several subtrees such that every subtree has equal path length and all source-to-sink paths have an equal number of levels. Clock gating is another well-known technique in reducing the dynamic power dissipation of a digital circuit [reference 5 and 6]. It saves power by shutting off the sequential elements and part of the clock network during an idle state.
The design of the clock distribution network also determines the clock skew. The clock skew directly affects chip performance in a close to one-to-one ratio, since it has to be counted as a cycletime penalty. The clock trees need to be incrementally adjusted accordingly with minimum changes to ensure an acceptable clock skew. The buffer insertion usually deals with the clock skew minimization problem [reference 7]. Other research using the buffer insertion method minimizes both the power consumption and the clock skew criterion [reference 4].